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PhD Student / Research Assistant (f/m/d)
Timing Guarantees and Optimizations for Systems with Non-volatile Memories

Organisationseinheit

Institut für Technische Informatik (ITEC)

Ihre Aufgaben

Since many years, the Chair for Embedded Systems works internationally successfully in the areas of computer engineering, such as smart embedded systems. Many interesting and open problems in these areas need to be addressed to successfully deploy such systems in modern application domains. As an example, the most urgent questions about memory architectures in real-time systems are highlighted in the following.

Embedded systems and real-time systems are ubiquitous in our everyday life, e.g., in safety-critical domains such as automotive or avionics, or in smart IoT-based environments such as environmental monitoring or smart wearables. However, embedded systems usually have limited energy, computing power, and memory/storage space. The emerging byte-addressable non-volatile memories (referred to as NVMs for short), such as Phase Change Memory (PCM), Spin-Transfer Torque RAM (STT-RAM) and Resistive RAM (ReRAM), feature low leakage power, high density, and low unit costs. NVMs are hence interesting alternatives to replace DRAM as main memory or hard disks and NAND flash as storage. In a recent project, we investigate a visionary system architecture that uses NVMs to replace both, DRAM and storage (called “one-memory architecture”), to avoid the high power requirements of DRAM and the conceptually unnecessary data transfers between DRAM and storage. That is, the storage (i.e., file system) and the working memory (i.e., main memory) both reside in one NVM. However, that also comes with several challenges.

The correctness of a real-time system does not only depend on the correctness of its calculations, but also on the non-functional requirement of adhering to timing deadlines. Failing to meet a deadline may lead to severe malfunctions or even threaten life, therefore there need to be guarantees in a process called timing validation. As part of the timing validation, a schedulability analysis is performed to guarantee that a given task set can be scheduled at runtime under any circumstances, and to perform a schedulability analysis, the worst-case execution time (WCET) of every task from the task set needs to be known. For the WCET analysis, a safe upper bound of memory accesses needs to be statically known, which is possible for DRAM, but challenging for NVMs. For instance, to avoid wearing out the NVM cells too fast, wear-levelling approaches are typically used to redistribute memory accesses across the storage, which involves copying data, which costs time. It is demanding to guarantee statically, when an application will face a delay due to wear-levelling operations, and therefore it is challenging to guarantee a safe and tight upper bound of its WCET.

In the scope of this research project, we want to investigate: WCET analysis for systems with NVM memory, optimizations for applications running on those systems (e.g. trading execution time with data retention time), hardware implementations for wear-levelling approaches, FPGA-based runtime reconfiguration to switch between system services (wear levelling) and application-specific accelerators, WCET analysis of hardware accelerators, in-/near-memory computing approaches, etc.

Further details can be found on our webpage: ces.itec.kit.edu.

Eintrittstermin

as soon as possible

Ihre Qualifikation

The candidate (f/m/d) must have a very good Master's degree (or equivalent) in CS or EE with background or specialization in some of the above-mentioned topics, i.e., NVM, WCET analysis, hardware-/software co-design, and/or embedded systems. The ideal candidate (f/m/d) shows a strong interest and motivation to deepen in these topics to a level required for a doctorate. Programming skills in C/C++ and VHDL/Verilog, and experience in synthesis tools, timing analysis tools, CPU/system simulators, and/or embedded operating systems will be very beneficial. Fluency in written and spoken English is a prerequisite. We are looking for a highly motivated candidate (f/m/d) with a strong commitment to research ethics and teamwork. Good communicative skills are mandatory due to the interdisciplinary structure of the project and the team.

Salary

Salary category EG 13, depending on the fulfillment of professional and personal requirements.

Contract duration

limited for 1 year with the possibility for multi-year extension

Application up to

January 15, 2023

Contact person in line-management

For further information, please contact Prof. Henkel, email: henkel@kit.edu and Dr. Bauer, email: lars.bauer@kit.edu.

Application

Please send your application including a cover letter, your CV, and all certificates/referees in electronic form to: lars.bauer@kit.edu.

vacancy number: 2290/2022

We prefer to balance the number of employees (f/m/d). Therefore, we kindly ask also female applicants to apply for this job.

Recognized severely disabled persons will be preferred if they are equally qualified.