08-2021-IPE PhD Position in Electrical Engineering: Innovative silicon pixel detector for future experiments
Institute for Data Processing and Electronics (IPE)
Progress in experimental physics relies often on advances and breakthroughs in instrumentation, leading to substantial gains in measurement accuracy, efficiency and speed, or even opening completely new approaches and methods. We are proposing a novel and radical vision of silicon pixel/strip detector, which goes well beyond the current hybrid or monolithic pixel architectures. In our proposal, the detector is based on resistive AC-coupled LGADs (RSD). The RSD is an evolution of the standard LGAD (Low-Gain Avalanche Diode) technology, where a resistive n-type implant and a coupling dielectric layer have been implemented, and an excellent gain uniformity even at a fill-factor of 100% (see Fig. 1) is achieved. The thin substrate of the RSD sensor combined with a back thinned readout chip will result in an ultra-low material budget, similar to the one of a monolithic pixel detector, but with superior performance in terms of signal-to-noise, spatial and time resolution. The aim to increase in-pixel functionality in future pixel detector ASICs and the requirement for high position, time and energy accuracy requires a breakthrough in both ASIC technology and readout architecture. Modern technologies can be very radiation-hard even at ultra-high TID. The novel 28 nm CMOS technology has become affordable during the last years and it is expected to become soon one of the major new technology for future pixel and strip detectors.
Figure 2. Each pixel of an RSD event carries a lot of information (amplitude, arrive time, time-over-threshold, etc.). The pixels information will be processed by a machine learning circuit shared between groups of adjacent pixels.
Machine learning (ML) is ideal for optimizing complex, non-linear systems and, in multidimensional parameter spaces, for optimizing them efficiently according to given performance parameters. Each event in an RSD carries multiple types of information (amplitude, derivative, width) that can be used to perform accurate x-y-t reconstruction. To improve both spatial and time measurements, we are proposing a radical novel readout scheme, where the pixels are read out and processed by an artificial intelligence circuit connected to adjacent pixel. The results will be a very accurate x-y-t reconstruction and an inherent data reduction.
- Explore and perform the noise analysis of several input stages based on input impedance-controlled gate-amplifiers and compare the performance with a classic charge-sensitive-amplifier.
- Design and submit of an ASICs chip with several front-end candidate architectures and perform both the noise and signals measurements.
- Investigation and development of a work-flow for the deployment of ML data processing on ASICs.
- Optimization, final submission and measurement of an ASIC for a selected application in realistic experimental conditions.
The thesis requires in-depth R&D on advanced design, the submission of microcircuits in TSMC 28nm technology and the noise characterization. The research plan includes the design of microelectronics and its test & validation. Scientific publication are part of the PhD process. The research activities are embedded in the international ASICs detector community with our partners at CERN, INFN and Fermilab. Supervision of bachelor and master students, the presentations of results at scientific conferences, and publishing articles in high-impact journal is expected.
as soon as possible
A master degree in Electrical Engineering, physics or equivalent is required. Experience in the development of fast neural network inference on FPGA is an advantage. You should be comfortable in specifying system components and possess sound experimental problem-solving skills. You are a naturally curious person who is eager to learn fast and have a strong interest in research. Good English language proficiency is essential, basic German language skills are of advantage.
limited to 3 years
Application up to
31 May 2021
Contact person in line-management
For further information, please contact Dr.-Ing. Michele Caselle, phone 0721 608-25903; Mail: email@example.com
Please apply online using the button below for this vacancy number 08-2021-IPE.
We prefer to balance the number of employees (f/m/d). Therefore we kindly ask female applicants to apply for this job.
Recognized severely disabled persons will be preferred if they are equally qualified.
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