29-2020-IPE PhD Position: Design and characterization of novel ASICs technology for future collider experiments
Institute for Data Processing and Electronics (IPE)
Technology innovation in electronics has always been a fundamental step towards the conception of new experimental techniques in nuclear, particle and hadron physics or of novel detectors. The front-end electronics is a fundamental part of any detector system, and fulfils the task of collecting, amplifying, storing and processing the signal coming from the sensor and reading it out to the back-end electronics for further digital processing. The next generation of detectors will operate at an unprecedented peak luminosity, leading to extreme pile-up, track density, radiation loads and data throughput. The detector instrumentation community is currently designing in 130 nm and 65 nm commercial-grade CMOS technologies. Novel smaller feature size processes offer potential advantages like superior functionality and higher speed Fully-depleted Silicon on Insulator (FD-SOI) is an emerging planar process technology that relies on two primary innovations. First, an ultra-thin layer of insulator, called the buried oxide, is positioned on top of the base silicon. Then, a very thin silicon film implements the transistor channel. Due to its thinness, there is no need to dope the channel, thus making the transistor fully depleted. By design, FD-SOI enables much better transistor electrostatic characteristics compared to conventional bulk and FinFET technologies. It also efficiently confines the electrons flowing from the source to the drain, dramatically reducing performance-degrading leakage currents. The most important anticipated properties are: high radiation tolerance, superior analog /RF and digital performances, and very low power consumption. FD-SOI technology enables control of the behavior of transistors not only through the gate, but also by biasing the substrate underneath the device, so called body bias. This provides an extremely powerful technique to optimize performance and power consumption also after irradiation. The body bias can be modulated dynamically during transistor operation, bringing a great flexibility in the mitigation of the positive charge trapped inside both the gate and the thin buried oxide induced by the irradiation. The PhD work will focus on investigation and characterization of 12 and 22 nm FD-SOI technology, the following task are required:
- Design and submission of an ASIC with several p- and n-MOS transistors with different features in FD-SOI, test and characterization, including the noise, before and after the irradiation at several beam sources.
- Design and submission of an ASICs with statics and dynamic memories, analog and digital circuits in FD-SOI technology, test and characterization of the total dose and single-event- upset effect.
- Design a complete readout circuit ready for implementation in a detector system.
There are many aspects of this project, which will require in-depth R&D. This includes advanced design and submission of microcircuits in novel and advanced sub-nanometer CMOS technology, characterization of CMOS technology before and after irradiation with protons and x-rays. The research plan includes the design of microelectronics, test & validation and scientific publication are part of the PhD process. The research activity will be embedded within the ASICs detector community i.e. CERN, Fraunhofer Institute, Global Foundries and INFN. Supervision of bachelor and master students, presentations at scientific conferences, and writing high-impact journal articles is expected.
as soon as possible
A master degree in Electrical Engineering, physics or equivalent is required. Experience in ASICs design is a definite advantage, as well as being comfortable in specifying system components and sound experimental problem-solving skills. You are a naturally curious person who is eager to learn fast and has a strong interest in research. Good English language proficiency is essential, basic German language skills are of advantage.
limited to 3 years
Application up to
28 February 2021
Contact person in line-management
For further information, please contact Dr.-Ing. Michele Caselle, phone 0721 608-25903; Mail: email@example.com
Please apply online using the button below for this vacancy number 29-2020-IPE.
Recognized severely disabled persons will be preferred if they are equally qualified.
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Phone: +49 721 608-25006,
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