IPE 17-20 Masterthesis: A Terabit sampling system with a photonics time-stretch analog-to-digital converter
Institute for Data Processing and Electronics (IPE)
of ultrafast events. Commercially available real-time equipment is limited in bandwidth (240 GS/s, LeCroy LabMaster 10-100Zi) and cannot be used to characterize these events in the pico-and femtosecond regime. In this thesis you will evaluate a real-time measurement technique based on the photonic time-stretch analog-to-digital converter (TS-ADC) for the measurement of ultrafast signals with a sampling-rate which exceeds TS/s. The principle is to use a photonic front-end that effectively “slows down” the analog signal in time before it is digitized by fast ADCs.
The proposed concept can be realized using the recent RFSoC Zynq FPGA family, that combines an array of multi-channels GS/s of fast-ADCs with a Field Programmable Gate Array (FPGA). The stretched optical pulse is sampled by 16 parallel ADCs operating in time-interleaving mode. The sampled data is then transmitted by a 400 Gbit ethernet data link to the DAQ compute node. You will develop a first demonstrator of a TS-ADC operating at several TS/s and integrate it in one of our experimental stations. At the end of the thesis, you will have gained valuable knowledge on the design and commissioning of cutting-edge data acquisition systems demanded in academia and industry.
as soon as possible
- Study the TS-ADC concept
- Setup a first demonstrator with a RFSoC Zynq FPGA.
- Integration the demonstrator at the experimental stations in SOLEIL, France and/or at KIT, Germany
- Optimization and documentation of the results
The thesis will be supervised in collaboration with the PhLAM laboratory for photonics aspects (France).The main part of the work (electronics and software development) is located at KIT. Travel to Lille University is expected for developing and testing the whole photonic time-stretch system, using a terahertz waveform source. Travel to the SOLEIL synchrotron radiation facility is also foreseen (depending on the project and accelerator schedules).
- Knowledge in C and Verilog/VHDL (basic)
- Embedded and hardware programming (better but not required)
- Previous experience with developing for a Xilinx Zynq SoC (better but not required)
limited regarding study regulations
Contact person in line-management
Dr.-Ing. Michele Caselle (IPE) (+49 721 608 25903), email: firstname.lastname@example.org
Prof. Dr. Serge Bielawski (+33 320434423), email: email@example.com
Please apply online using the button below for this vacancy number IPE 17-20.
Ausschreibungsnummer: IPE 17-20
If qualified, severely disabled persons will be preferred.
Personnel Support is provided by:
Phone: +49 721 608-25184,
Hermann-von-Helmholtz-Platz 1, 76344 Eggenstein-Leopoldshafen, Germany